Thursday, November 17, 2011

Intel’s ‘Knights Corner’ brings 1 TFLOPS from 50 cores on one chip

Intel has announced details of their next generation high-performance platforms, starting off with the Intel Xeon E5 processors. This new family of “Knights Corner” co-processors are the first in line to be developed on Intel’s new Many Integrated Core (Intel MIC) architecture, breaking the 1 Teraflop barrier.

The Knights Corner project came from Intel’s failed Larrabee microarchitecture that lost steam in face of Nvidia’s Tesla GPUs. Most of the supercomputers in the Top500 list use Intel Xeon’s (85%) or AMD Opteron processors in tandem with the Nvidia Tesla GPUs. However, with the Tesla GPUs involved, scientists have to write special codes where the processing is offloaded onto the GPUs. “With Knight’s Corner, the programming model that you’re using is the same programming model that you’re using on an AMD or a Xeon,” says Karl W. Schulz, associate director for application collaboration with the University of Texas at Austin’s Texas Advanced Computing Center. “You get good parallelism right out of the box, which is convenient,” he told Wired.

Intel's Technical Computing Group chief Raj Hazra holds a 1 teraflop Knights Corner chip.

Schulz is building a 10 petaflop supercomputer, called Stampede, which will be completed in 2013 and go head-to-head with the current Japanese, Fujitsu made “K Computer” 11 petaflop champion.

Back in 1996, the ASCI Red was the first supercomputer in the world to break the 1 teraflop barrier. Created using 72 server racks, the ASCI Red was used from 1997 to 2005 by the US government to maintain their nuclear arsenal. Now all of that power is available in the palm of your hands.

“It’s a reminder of how fast this industry moves,” says James Reinders, a parallel programming evangelist at Intel, who also spent two years working on ASCI Red. “I spent a lot of my life with a lot of my co-workers designing ASCI Red … to think that I can hold that in my hand now, it’s humbling.”

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